library IEEE;
use IEEE.std_logic_1164.all;


entity INV_BLOCK is   -- INV_BLOCK 
        port (  
                CLOCK, WR		: in std_logic; 
				INV				: out std_logic
        );
end INV_BLOCK ;


architecture INV_MAIN of INV_BLOCK is
begin
        process (CLOCK, WR)        
        begin
			if(WR='1') then
                if(CLOCK'event and CLOCK='0') then
					INV <= '1';
				else
					INV <= '0';
				end if;
			else
				INV <= '0';
			end if;
        end process;
end INV_MAIN;


