Classic Timing Analyzer report for Arbitration
Fri Apr 11 04:58:53 2014
Quartus II Version 9.1 Build 222 10/21/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. Clock Setup: 'CLOCK'
  7. Clock Hold: 'CLOCK'
  8. tco
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                         ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                                                                                                         ; To                                                                                                           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tco               ; N/A                                      ; None          ; 15.466 ns                        ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; DATA[4]                                                                                                      ; CLOCK      ; --       ; 0            ;
; Clock Setup: 'CLOCK'         ; N/A                                      ; None          ; 177.40 MHz ( period = 5.637 ns ) ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; CLOCK      ; CLOCK    ; 0            ;
; Clock Hold: 'CLOCK'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; 81           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                                              ;                                                                                                              ;            ;          ; 81           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; Off                ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK'                                                                                                                                                                                                                                                                                                                                                                             ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                         ; To                                                                                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 177.40 MHz ( period = 5.637 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 1.229 ns                ;
; N/A   ; 179.73 MHz ( period = 5.564 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 1.156 ns                ;
; N/A   ; 179.79 MHz ( period = 5.562 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 1.154 ns                ;
; N/A   ; 186.12 MHz ( period = 5.373 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.965 ns                ;
; N/A   ; 186.46 MHz ( period = 5.363 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.890 ns                ;
; N/A   ; 187.34 MHz ( period = 5.338 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.930 ns                ;
; N/A   ; 187.69 MHz ( period = 5.328 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.855 ns                ;
; N/A   ; 187.69 MHz ( period = 5.328 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.855 ns                ;
; N/A   ; 187.69 MHz ( period = 5.328 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.920 ns                ;
; N/A   ; 188.57 MHz ( period = 5.303 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.895 ns                ;
; N/A   ; 188.93 MHz ( period = 5.293 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; 188.93 MHz ( period = 5.293 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; 188.93 MHz ( period = 5.293 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.885 ns                ;
; N/A   ; 189.83 MHz ( period = 5.268 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.860 ns                ;
; N/A   ; 190.19 MHz ( period = 5.258 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 190.19 MHz ( period = 5.258 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 190.19 MHz ( period = 5.258 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.850 ns                ;
; N/A   ; 191.09 MHz ( period = 5.233 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.825 ns                ;
; N/A   ; 191.28 MHz ( period = 5.228 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; 191.46 MHz ( period = 5.223 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 191.46 MHz ( period = 5.223 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 191.46 MHz ( period = 5.223 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.815 ns                ;
; N/A   ; 192.09 MHz ( period = 5.206 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.890 ns                ;
; N/A   ; 192.38 MHz ( period = 5.198 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.790 ns                ;
; N/A   ; 192.57 MHz ( period = 5.193 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 192.57 MHz ( period = 5.193 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 192.75 MHz ( period = 5.188 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 192.75 MHz ( period = 5.188 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 192.75 MHz ( period = 5.188 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.780 ns                ;
; N/A   ; 193.39 MHz ( period = 5.171 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.855 ns                ;
; N/A   ; 193.39 MHz ( period = 5.171 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.855 ns                ;
; N/A   ; 193.87 MHz ( period = 5.158 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 193.87 MHz ( period = 5.158 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 193.87 MHz ( period = 5.158 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 194.06 MHz ( period = 5.153 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 194.06 MHz ( period = 5.153 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.745 ns                ;
; N/A   ; 194.70 MHz ( period = 5.136 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; 194.70 MHz ( period = 5.136 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; 194.70 MHz ( period = 5.136 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; 195.20 MHz ( period = 5.123 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 195.20 MHz ( period = 5.123 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 195.20 MHz ( period = 5.123 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 195.20 MHz ( period = 5.123 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 196.04 MHz ( period = 5.101 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 196.04 MHz ( period = 5.101 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 196.04 MHz ( period = 5.101 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 196.54 MHz ( period = 5.088 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 196.54 MHz ( period = 5.088 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 196.54 MHz ( period = 5.088 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 196.54 MHz ( period = 5.088 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 196.54 MHz ( period = 5.088 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 197.39 MHz ( period = 5.066 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 197.39 MHz ( period = 5.066 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 197.39 MHz ( period = 5.066 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 198.77 MHz ( period = 5.031 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 198.77 MHz ( period = 5.031 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 199.32 MHz ( period = 5.017 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 199.32 MHz ( period = 5.017 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 199.32 MHz ( period = 5.017 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 199.32 MHz ( period = 5.017 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 199.32 MHz ( period = 5.017 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 199.32 MHz ( period = 5.017 ns )               ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 200.16 MHz ( period = 4.996 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 306.00 MHz ( period = 3.268 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 309.31 MHz ( period = 3.233 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 309.31 MHz ( period = 3.233 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 309.89 MHz ( period = 3.227 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; 312.70 MHz ( period = 3.198 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 312.70 MHz ( period = 3.198 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 312.70 MHz ( period = 3.198 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 312.70 MHz ( period = 3.198 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 313.28 MHz ( period = 3.192 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 313.28 MHz ( period = 3.192 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; 316.16 MHz ( period = 3.163 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 316.16 MHz ( period = 3.163 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 316.16 MHz ( period = 3.163 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 316.16 MHz ( period = 3.163 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 316.16 MHz ( period = 3.163 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 316.16 MHz ( period = 3.163 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 316.76 MHz ( period = 3.157 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 316.76 MHz ( period = 3.157 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 316.76 MHz ( period = 3.157 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; 320.31 MHz ( period = 3.122 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 320.31 MHz ( period = 3.122 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 320.31 MHz ( period = 3.122 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 320.31 MHz ( period = 3.122 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; 323.42 MHz ( period = 3.092 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 323.42 MHz ( period = 3.092 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 323.42 MHz ( period = 3.092 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 323.42 MHz ( period = 3.092 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 323.42 MHz ( period = 3.092 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 323.42 MHz ( period = 3.092 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 323.42 MHz ( period = 3.092 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 323.42 MHz ( period = 3.092 ns )               ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 323.94 MHz ( period = 3.087 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 323.94 MHz ( period = 3.087 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 323.94 MHz ( period = 3.087 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 323.94 MHz ( period = 3.087 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 323.94 MHz ( period = 3.087 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 323.94 MHz ( period = 3.087 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; 331.56 MHz ( period = 3.016 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 331.56 MHz ( period = 3.016 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 331.56 MHz ( period = 3.016 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 331.56 MHz ( period = 3.016 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 331.56 MHz ( period = 3.016 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 331.56 MHz ( period = 3.016 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 331.56 MHz ( period = 3.016 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; 331.56 MHz ( period = 3.016 ns )               ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.890 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.855 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.855 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                        ; None                      ; 0.609 ns                ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'CLOCK'                                                                                                                                                                                                                                                                                                                                                                 ;
+------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From                                                                                                         ; To                                                                                                           ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.745 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.750 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.750 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.750 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.780 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.785 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.785 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.790 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.815 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.820 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.825 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.850 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.860 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.885 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.895 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.920 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.930 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.965 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 1.154 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 1.156 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; CLOCK      ; CLOCK    ; None                       ; None                       ; 1.229 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.609 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.750 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.750 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.680 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.785 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.715 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.750 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.750 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.750 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.785 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.785 ns                 ;
; Not operational: Clock Skew > Data Delay ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; CLOCK      ; CLOCK    ; None                       ; None                       ; 0.820 ns                 ;
+------------------------------------------+--------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------+------------+------------+
; Slack                                   ; Required tco                                        ; Actual tco ; From                                                                                                         ; To         ; From Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------+------------+------------+
; N/A                                     ; None                                                ; 15.466 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 15.336 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 15.299 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 15.241 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 15.224 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 15.129 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 15.115 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 15.094 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 15.057 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.999 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.985 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 14.948 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 14.919 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.890 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 14.887 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.861 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.838 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.798 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.781 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.778 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 14.746 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.731 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.713 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; REQUEST[3] ; CLOCK      ;
; N/A                                     ; None                                                ; 14.708 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.694 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.677 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.671 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.668 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.636 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.631 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.613 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.583 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; REQUEST[3] ; CLOCK      ;
; N/A                                     ; None                                                ; 14.580 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.573 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.568 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 14.546 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; REQUEST[3] ; CLOCK      ;
; N/A                                     ; None                                                ; 14.541 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.539 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.532 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.524 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.504 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.501 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.488 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; REQUEST[3] ; CLOCK      ;
; N/A                                     ; None                                                ; 14.488 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.461 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.450 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.430 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 14.413 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.402 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.395 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 14.376 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; REQUEST[3] ; CLOCK      ;
; N/A                                     ; None                                                ; 14.365 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.355 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.314 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.307 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.291 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.283 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.251 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.243 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.195 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.176 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.166 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; REQUEST[3] ; CLOCK      ;
; N/A                                     ; None                                                ; 14.153 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.141 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.127 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 14.118 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.113 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.078 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.074 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 14.033 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 14.028 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; REQUEST[3] ; CLOCK      ;
; N/A                                     ; None                                                ; 13.993 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; REQUEST[3] ; CLOCK      ;
; N/A                                     ; None                                                ; 13.985 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.913 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.907 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.895 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.873 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.869 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 13.860 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.860 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.854 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.847 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.820 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.812 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.655 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.655 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.649 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.615 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.607 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.602 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.554 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.458 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7] ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.397 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.349 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.328 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6] ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.291 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4] ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.233 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0] ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 13.121 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5] ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.911 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2] ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.773 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1] ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.748 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.738 ns  ; MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3] ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.712 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.662 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.630 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.616 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.609 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.533 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.490 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; GRAND[1]   ; CLOCK      ;
; N/A                                     ; None                                                ; 12.480 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.469 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.466 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.437 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; GRAND[1]   ; CLOCK      ;
; N/A                                     ; None                                                ; 12.404 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.362 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.337 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.334 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 12.298 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 12.275 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[1]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.232 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; GRAND[1]   ; CLOCK      ;
; N/A                                     ; None                                                ; 12.216 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 12.202 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 12.180 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.153 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.120 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.114 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.084 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.080 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.078 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.055 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 12.052 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 12.044 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 12.002 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.996 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.988 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.982 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.968 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[4]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.962 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.950 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; GRAND[2]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.948 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.948 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.939 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.923 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.897 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; GRAND[2]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.862 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.841 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.838 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.832 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.826 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.814 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.807 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.801 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.798 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.778 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.766 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.744 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.739 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.734 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.730 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.728 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.709 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.696 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.694 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.692 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; GRAND[2]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.682 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.669 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.650 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.623 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.583 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.580 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.577 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.554 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; GRAND[3]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.552 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.535 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.532 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.525 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.512 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.485 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.476 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.451 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.445 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.438 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[5]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.428 ns  ; MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.405 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]  ; GRAND[1]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.403 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.365 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]  ; REQUEST[1] ; CLOCK      ;
; N/A                                     ; None                                                ; 11.340 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[3]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.312 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]  ; REQUEST[1] ; CLOCK      ;
; N/A                                     ; None                                                ; 11.300 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[7]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.294 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.288 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.273 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]  ; GRAND[1]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.267 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[2]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.261 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[6]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.246 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.219 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; DATA[0]    ; CLOCK      ;
; N/A                                     ; None                                                ; 11.116 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]  ; GRAND[1]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.107 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]  ; REQUEST[1] ; CLOCK      ;
; N/A                                     ; None                                                ; 11.089 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]  ; GRAND[1]   ; CLOCK      ;
; N/A                                     ; None                                                ; 11.082 ns  ; MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]  ; DATA[2]    ; CLOCK      ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                                                                                                              ;            ;            ;
+-----------------------------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 222 10/21/2009 SJ Web Edition
    Info: Processing started: Fri Apr 11 04:58:52 2014
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Arbitration -c Arbitration --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLOCK" is an undefined clock
Warning: Found 41 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]" as buffer
    Info: Detected gated clock "MASTER_DEVICE3:inst15|lpm_compare3:inst1|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~0" as buffer
    Info: Detected ripple clock "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]" as buffer
    Info: Detected gated clock "ARBITR:inst|inst8~0" as buffer
    Info: Detected gated clock "MASTER_DEVICE3:inst15|lpm_compare3:inst1|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~1" as buffer
    Info: Detected gated clock "MASTER_DEVICE3:inst15|inst19" as buffer
    Info: Detected ripple clock "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]" as buffer
    Info: Detected gated clock "MASTER_DEVICE2:inst3|lpm_compare2:inst3|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~0" as buffer
    Info: Detected gated clock "MASTER_DEVICE2:inst3|inst19" as buffer
    Info: Detected ripple clock "MASTER_DEVICE2:inst3|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[5]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[4]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]" as buffer
    Info: Detected ripple clock "MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[3]" as buffer
    Info: Detected gated clock "MASTER_DEVICE0:inst16|lpm_compare0:inst9|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~1" as buffer
    Info: Detected gated clock "MASTER_DEVICE0:inst16|lpm_compare0:inst9|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~0" as buffer
    Info: Detected gated clock "MASTER_DEVICE1:inst8|lpm_compare1:inst1|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~0" as buffer
    Info: Detected gated clock "MASTER_DEVICE1:inst8|lpm_compare1:inst1|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~1" as buffer
    Info: Detected gated clock "MASTER_DEVICE1:inst8|inst19" as buffer
    Info: Detected ripple clock "MASTER_DEVICE1:inst8|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]" as buffer
Info: Clock "CLOCK" has Internal fmax of 177.4 MHz between source register "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]" and destination register "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]" (period= 5.637 ns)
    Info: + Longest register to register delay is 1.229 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y2_N21; Fanout = 4; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]'
        Info: 2: + IC(0.224 ns) + CELL(0.309 ns) = 0.533 ns; Loc. = LCCOMB_X17_Y2_N0; Fanout = 2; COMB Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|counter_comb_bita0~COUT'
        Info: 3: + IC(0.000 ns) + CELL(0.125 ns) = 0.658 ns; Loc. = LCCOMB_X17_Y2_N2; Fanout = 1; COMB Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|counter_comb_bita1'
        Info: 4: + IC(0.262 ns) + CELL(0.309 ns) = 1.229 ns; Loc. = LCFF_X17_Y2_N31; Fanout = 4; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]'
        Info: Total cell delay = 0.743 ns ( 60.46 % )
        Info: Total interconnect delay = 0.486 ns ( 39.54 % )
    Info: - Smallest clock skew is -4.224 ns
        Info: + Shortest clock path from clock "CLOCK" to destination register is 4.908 ns
            Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_Y12; Fanout = 4; CLK Node = 'CLOCK'
            Info: 2: + IC(0.828 ns) + CELL(0.053 ns) = 1.690 ns; Loc. = LCCOMB_X17_Y2_N26; Fanout = 1; COMB Node = 'MASTER_DEVICE3:inst15|inst19'
            Info: 3: + IC(1.943 ns) + CELL(0.000 ns) = 3.633 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'MASTER_DEVICE3:inst15|inst19~clkctrl'
            Info: 4: + IC(0.657 ns) + CELL(0.618 ns) = 4.908 ns; Loc. = LCFF_X17_Y2_N31; Fanout = 4; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[1]'
            Info: Total cell delay = 1.480 ns ( 30.15 % )
            Info: Total interconnect delay = 3.428 ns ( 69.85 % )
        Info: - Longest clock path from clock "CLOCK" to source register is 9.132 ns
            Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_Y12; Fanout = 4; CLK Node = 'CLOCK'
            Info: 2: + IC(0.890 ns) + CELL(0.053 ns) = 1.752 ns; Loc. = LCCOMB_X18_Y3_N2; Fanout = 8; COMB Node = 'MASTER_DEVICE0:inst16|inst19'
            Info: 3: + IC(0.215 ns) + CELL(0.712 ns) = 2.679 ns; Loc. = LCFF_X18_Y3_N29; Fanout = 3; REG Node = 'MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]'
            Info: 4: + IC(0.258 ns) + CELL(0.346 ns) = 3.283 ns; Loc. = LCCOMB_X18_Y3_N4; Fanout = 7; COMB Node = 'MASTER_DEVICE0:inst16|lpm_compare0:inst9|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~1'
            Info: 5: + IC(0.956 ns) + CELL(0.346 ns) = 4.585 ns; Loc. = LCCOMB_X19_Y11_N30; Fanout = 6; COMB Node = 'ARBITR:inst|inst8~0'
            Info: 6: + IC(1.104 ns) + CELL(0.225 ns) = 5.914 ns; Loc. = LCCOMB_X17_Y2_N26; Fanout = 1; COMB Node = 'MASTER_DEVICE3:inst15|inst19'
            Info: 7: + IC(1.943 ns) + CELL(0.000 ns) = 7.857 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'MASTER_DEVICE3:inst15|inst19~clkctrl'
            Info: 8: + IC(0.657 ns) + CELL(0.618 ns) = 9.132 ns; Loc. = LCFF_X17_Y2_N21; Fanout = 4; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[0]'
            Info: Total cell delay = 3.109 ns ( 34.05 % )
            Info: Total interconnect delay = 6.023 ns ( 65.95 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Micro setup delay of destination is 0.090 ns
Warning: Circuit may not operate. Detected 81 non-operational path(s) clocked by clock "CLOCK" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]" and destination pin or register "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]" for clock "CLOCK" (Hold time is 3.67 ns)
    Info: + Largest clock skew is 4.224 ns
        Info: + Longest clock path from clock "CLOCK" to destination register is 9.132 ns
            Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_Y12; Fanout = 4; CLK Node = 'CLOCK'
            Info: 2: + IC(0.890 ns) + CELL(0.053 ns) = 1.752 ns; Loc. = LCCOMB_X18_Y3_N2; Fanout = 8; COMB Node = 'MASTER_DEVICE0:inst16|inst19'
            Info: 3: + IC(0.215 ns) + CELL(0.712 ns) = 2.679 ns; Loc. = LCFF_X18_Y3_N29; Fanout = 3; REG Node = 'MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]'
            Info: 4: + IC(0.258 ns) + CELL(0.346 ns) = 3.283 ns; Loc. = LCCOMB_X18_Y3_N4; Fanout = 7; COMB Node = 'MASTER_DEVICE0:inst16|lpm_compare0:inst9|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~1'
            Info: 5: + IC(0.956 ns) + CELL(0.346 ns) = 4.585 ns; Loc. = LCCOMB_X19_Y11_N30; Fanout = 6; COMB Node = 'ARBITR:inst|inst8~0'
            Info: 6: + IC(1.104 ns) + CELL(0.225 ns) = 5.914 ns; Loc. = LCCOMB_X17_Y2_N26; Fanout = 1; COMB Node = 'MASTER_DEVICE3:inst15|inst19'
            Info: 7: + IC(1.943 ns) + CELL(0.000 ns) = 7.857 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'MASTER_DEVICE3:inst15|inst19~clkctrl'
            Info: 8: + IC(0.657 ns) + CELL(0.618 ns) = 9.132 ns; Loc. = LCFF_X17_Y2_N5; Fanout = 4; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]'
            Info: Total cell delay = 3.109 ns ( 34.05 % )
            Info: Total interconnect delay = 6.023 ns ( 65.95 % )
        Info: - Shortest clock path from clock "CLOCK" to source register is 4.908 ns
            Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_Y12; Fanout = 4; CLK Node = 'CLOCK'
            Info: 2: + IC(0.828 ns) + CELL(0.053 ns) = 1.690 ns; Loc. = LCCOMB_X17_Y2_N26; Fanout = 1; COMB Node = 'MASTER_DEVICE3:inst15|inst19'
            Info: 3: + IC(1.943 ns) + CELL(0.000 ns) = 3.633 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'MASTER_DEVICE3:inst15|inst19~clkctrl'
            Info: 4: + IC(0.657 ns) + CELL(0.618 ns) = 4.908 ns; Loc. = LCFF_X17_Y2_N5; Fanout = 4; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]'
            Info: Total cell delay = 1.480 ns ( 30.15 % )
            Info: Total interconnect delay = 3.428 ns ( 69.85 % )
    Info: - Micro clock to output delay of source is 0.094 ns
    Info: - Shortest register to register delay is 0.609 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y2_N5; Fanout = 4; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]'
        Info: 2: + IC(0.000 ns) + CELL(0.512 ns) = 0.512 ns; Loc. = LCCOMB_X17_Y2_N4; Fanout = 1; COMB Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|counter_comb_bita2'
        Info: 3: + IC(0.000 ns) + CELL(0.097 ns) = 0.609 ns; Loc. = LCFF_X17_Y2_N5; Fanout = 4; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[2]'
        Info: Total cell delay = 0.609 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 0.149 ns
Info: tco from clock "CLOCK" to destination pin "DATA[4]" through register "MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]" is 15.466 ns
    Info: + Longest clock path from clock "CLOCK" to source register is 9.132 ns
        Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_Y12; Fanout = 4; CLK Node = 'CLOCK'
        Info: 2: + IC(0.890 ns) + CELL(0.053 ns) = 1.752 ns; Loc. = LCCOMB_X18_Y3_N2; Fanout = 8; COMB Node = 'MASTER_DEVICE0:inst16|inst19'
        Info: 3: + IC(0.215 ns) + CELL(0.712 ns) = 2.679 ns; Loc. = LCFF_X18_Y3_N29; Fanout = 3; REG Node = 'MASTER_DEVICE0:inst16|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[6]'
        Info: 4: + IC(0.258 ns) + CELL(0.346 ns) = 3.283 ns; Loc. = LCCOMB_X18_Y3_N4; Fanout = 7; COMB Node = 'MASTER_DEVICE0:inst16|lpm_compare0:inst9|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~1'
        Info: 5: + IC(0.956 ns) + CELL(0.346 ns) = 4.585 ns; Loc. = LCCOMB_X19_Y11_N30; Fanout = 6; COMB Node = 'ARBITR:inst|inst8~0'
        Info: 6: + IC(1.104 ns) + CELL(0.225 ns) = 5.914 ns; Loc. = LCCOMB_X17_Y2_N26; Fanout = 1; COMB Node = 'MASTER_DEVICE3:inst15|inst19'
        Info: 7: + IC(1.943 ns) + CELL(0.000 ns) = 7.857 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'MASTER_DEVICE3:inst15|inst19~clkctrl'
        Info: 8: + IC(0.657 ns) + CELL(0.618 ns) = 9.132 ns; Loc. = LCFF_X17_Y2_N15; Fanout = 2; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]'
        Info: Total cell delay = 3.109 ns ( 34.05 % )
        Info: Total interconnect delay = 6.023 ns ( 65.95 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 6.240 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y2_N15; Fanout = 2; REG Node = 'MASTER_DEVICE3:inst15|lpm_counter0:inst7|lpm_counter:lpm_counter_component|cntr_04i:auto_generated|safe_q[7]'
        Info: 2: + IC(0.261 ns) + CELL(0.346 ns) = 0.607 ns; Loc. = LCCOMB_X17_Y2_N20; Fanout = 1; COMB Node = 'MASTER_DEVICE3:inst15|lpm_compare3:inst1|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~0'
        Info: 3: + IC(0.500 ns) + CELL(0.053 ns) = 1.160 ns; Loc. = LCCOMB_X17_Y2_N28; Fanout = 8; COMB Node = 'MASTER_DEVICE3:inst15|lpm_compare3:inst1|lpm_compare:lpm_compare_component|cmpr_tbj:auto_generated|ageb~1'
        Info: 4: + IC(0.271 ns) + CELL(0.346 ns) = 1.777 ns; Loc. = LCCOMB_X17_Y2_N18; Fanout = 8; COMB Node = 'MASTER_DEVICE1:inst8|inst20[7]~5'
        Info: 5: + IC(2.343 ns) + CELL(2.120 ns) = 6.240 ns; Loc. = PIN_J5; Fanout = 0; PIN Node = 'DATA[4]'
        Info: Total cell delay = 2.865 ns ( 45.91 % )
        Info: Total interconnect delay = 3.375 ns ( 54.09 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 131 megabytes
    Info: Processing ended: Fri Apr 11 04:58:53 2014
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


