library IEEE;
use IEEE.std_logic_1164.all;


entity SAVE_BLOCK is   -- SAVE_BLOCK 
        port (  
                CLOCK, WR		: in std_logic; 
				SAVE				: out std_logic
        );
end SAVE_BLOCK ;


architecture SAVE_MAIN of SAVE_BLOCK is
begin
        process (CLOCK, WR)        
        begin        
			if(WR='1') then
                if(CLOCK'event and CLOCK='0') then
					SAVE <= '1';
				end if;
			else
				SAVE <= '0';
			end if;
        end process;
end SAVE_MAIN;


