library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;


entity COUNTER_BLOCK is   -- COUNTER_BLOCK 
        port (  
                CLOCK				: in std_logic; 
                A					: in std_logic_vector(15 downto 0);
				B					: in std_logic_vector(15 downto 0);
				A_bin				: out std_logic_vector(3 downto 0);
				B_bin				: out std_logic_vector(3 downto 0)
        );
end COUNTER_BLOCK ;


architecture COUNTER_MAIN of COUNTER_BLOCK is

begin
        process (CLOCK)   
        variable  i: natural := 0;   
        variable A1: integer := 0;  
        variable A2: integer := 0;
        begin
			i  := 0;
			if(CLOCK='1') then
                while i <= 15 loop
					if(A(i)='1') then
						A1 := A1 + 1;
					end if;
					if(B(i)='1') then
						A2 := A2 + 1;
					end if;
					i := i + 1;
				end loop;				
			end if;
			A_bin <= CONV_STD_LOGIC_VECTOR(A1, 4);
			B_bin <= CONV_STD_LOGIC_VECTOR(A2, 4);
        end process;
end COUNTER_MAIN;


