library IEEE;
use IEEE.std_logic_1164.all;


entity MUX_BLOCK is   -- MUX_BLOCK 
        port (  
                IN_0, IN_1, SEL	: in std_logic; 
				MUX				: out std_logic
        );
end MUX_BLOCK ;


architecture MUX_MAIN of MUX_BLOCK is
begin
        process (SEL)        
        begin
			if(SEL='1') then
                MUX <= IN_1;
			else
				MUX <= IN_0;
			end if;
        end process;
end MUX_MAIN;


