library IEEE;
use IEEE.std_logic_1164.all;


entity UP_BLOCK is   -- UP_BLOCK 
        port (  
                CLOCK			: in std_logic; 
                QQ				: in std_logic_vector(1 downto 0);
				UP				: out std_logic
        );
end UP_BLOCK ;


architecture UP_MAIN of UP_BLOCK is
begin
        process (QQ)        
        begin        
            if(QQ="10") then
				UP <= not(CLOCK);
			else
				UP <= '0';
			end if;
        end process;
end UP_MAIN;


