library IEEE;
use IEEE.std_logic_1164.all;


entity DEC_BLOCK is   -- DEC_BLOCK 
        port (  
                CLOCK, WR		: in std_logic; 
				DEC				: out std_logic
        );
end DEC_BLOCK ;


architecture DEC_MAIN of DEC_BLOCK is
begin
        process (CLOCK, WR)        
        begin
			if(WR='1' and WR'stable(10 ns)) then
                DEC <= CLOCK;				
			else
				DEC <= '0';
			end if;
        end process;
end DEC_MAIN;


