library IEEE;
use IEEE.std_logic_1164.all;


entity DEC_BLOCK is   -- DEC_BLOCK 
        port (  
                CLOCK, ACLR, DELAY		: in std_logic; 
				DEC						: out std_logic
        );
end DEC_BLOCK ;


architecture DEC_MAIN of DEC_BLOCK is
begin
	DEC <= (not(CLOCK)) and ((not(ACLR)) and (not(DELAY)));
end DEC_MAIN;


