library IEEE;
use IEEE.std_logic_1164.all;


entity ACLR_BLOCK is   -- ACLR_BLOCK 
        port (  
                ON_IN, CLOCK	: in std_logic; 
				ACLR 			: out std_logic
        );
end ACLR_BLOCK ;


architecture ACLR_MAIN of ACLR_BLOCK is
begin
        process (ON_IN, CLOCK)        
        begin
			if(ON_IN='1') then
                if(CLOCK'event and CLOCK='1') then
					ACLR <= '1';
				end if;
			else
				ACLR <= '0';
			end if;
        end process;
end ACLR_MAIN;


