-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 9.1 (Build Build 222 10/21/2009)
-- Created on Thu May 09 21:20:48 2013

COMPONENT RAM_ROM_BIDIR
	GENERIC ( ROM/RAM : STRING := "0/1" );
	PORT
	(
		CLOCK		:	 IN STD_LOGIC;
		ROM		:	 IN STD_LOGIC;
		ADDR		:	 IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		WRITE_ON		:	 IN STD_LOGIC;
		IN_OUT		:	 INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END COMPONENT;