library IEEE;
use IEEE.std_logic_1164.all;


entity UP_BLOCK is   -- UP_BLOCK 
        port (  
                CLOCK		: in std_logic; 
				UP				: out std_logic
        );
end UP_BLOCK ;


architecture UP_MAIN of UP_BLOCK is
begin
        process (CLOCK, WR)        
        begin        
			if(WR='1') then
                if(CLOCK'event and CLOCK='0') then
					UP <= '1';
				end if;
			else
				UP <= '0';
			end if;
        end process;
end UP_MAIN;


