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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 82.928 ns
From           : DMA_DATA_BIDIR[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst21|lpm_ff:lpm_ff_component|dffs[4]
From Clock     : --
To Clock       : CLOCK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 1181.400 ns
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : DATA[6]
From Clock     : CLOCK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 89.008 ns
From           : DMA_DATA_BIDIR[2]
To             : DATA[2]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1092.288 ns
From           : CLOCK
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[7]
From Clock     : --
To Clock       : CLOCK
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK'
Slack          : N/A
Required Time  : None
Actual Time    : 0.43 MHz ( period = 2327.334 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : CACHE_BLOCK:inst5|CACHE_CONTROL:inst1|IN_CACHE[1]
From Clock     : CLOCK
To Clock       : CLOCK
Failed Paths   : 0

Type           : Clock Setup: 'DMA_WRITE'
Slack          : N/A
Required Time  : None
Actual Time    : 0.91 MHz ( period = 1093.523 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[6]
From Clock     : DMA_WRITE
To Clock       : DMA_WRITE
Failed Paths   : 0

Type           : Clock Setup: 'DMA_CLOCK'
Slack          : N/A
Required Time  : None
Actual Time    : 0.92 MHz ( period = 1091.648 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[6]
From Clock     : DMA_CLOCK
To Clock       : DMA_CLOCK
Failed Paths   : 0

Type           : Clock Setup: 'DMA_DATA_BIDIR[7]'
Slack          : N/A
Required Time  : None
Actual Time    : 0.93 MHz ( period = 1078.813 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst74|lpm_ff:lpm_ff_component|dffs[4]
From Clock     : DMA_DATA_BIDIR[7]
To Clock       : DMA_DATA_BIDIR[7]
Failed Paths   : 0

Type           : Clock Setup: 'DMA_DATA_BIDIR[1]'
Slack          : N/A
Required Time  : None
Actual Time    : 0.94 MHz ( period = 1068.128 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[6]
From Clock     : DMA_DATA_BIDIR[1]
To Clock       : DMA_DATA_BIDIR[1]
Failed Paths   : 0

Type           : Clock Setup: 'DMA_DATA_BIDIR[3]'
Slack          : N/A
Required Time  : None
Actual Time    : 0.95 MHz ( period = 1056.663 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst4|lpm_ff:lpm_ff_component|dffs[4]
From Clock     : DMA_DATA_BIDIR[3]
To Clock       : DMA_DATA_BIDIR[3]
Failed Paths   : 0

Type           : Clock Setup: 'DMA_DATA_BIDIR[6]'
Slack          : N/A
Required Time  : None
Actual Time    : 0.96 MHz ( period = 1046.452 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[6]
From Clock     : DMA_DATA_BIDIR[6]
To Clock       : DMA_DATA_BIDIR[6]
Failed Paths   : 0

Type           : Clock Setup: 'DMA_DATA_BIDIR[5]'
Slack          : N/A
Required Time  : None
Actual Time    : 0.96 MHz ( period = 1046.452 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[6]
From Clock     : DMA_DATA_BIDIR[5]
To Clock       : DMA_DATA_BIDIR[5]
Failed Paths   : 0

Type           : Clock Setup: 'DMA_DATA_BIDIR[0]'
Slack          : N/A
Required Time  : None
Actual Time    : 0.96 MHz ( period = 1044.680 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst19|lpm_ff:lpm_ff_component|dffs[1]
From Clock     : DMA_DATA_BIDIR[0]
To Clock       : DMA_DATA_BIDIR[0]
Failed Paths   : 0

Type           : Clock Setup: 'DMA_DATA_BIDIR[2]'
Slack          : N/A
Required Time  : None
Actual Time    : 0.96 MHz ( period = 1038.530 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst3|lpm_ff:lpm_ff_component|dffs[6]
From Clock     : DMA_DATA_BIDIR[2]
To Clock       : DMA_DATA_BIDIR[2]
Failed Paths   : 0

Type           : Clock Setup: 'DMA_DATA_BIDIR[4]'
Slack          : N/A
Required Time  : None
Actual Time    : 0.96 MHz ( period = 1037.711 ns )
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[4]
From Clock     : DMA_DATA_BIDIR[4]
To Clock       : DMA_DATA_BIDIR[4]
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : DECODE_BLOCK:inst8|lpm_counter4:inst|lpm_counter:lpm_counter_component|cntr_ofi:auto_generated|safe_q[2]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
From Clock     : CLOCK
To Clock       : CLOCK
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_CLOCK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : RAM_ROM_BIDIR:inst1|lpm_ram_io:inst|altram:sram|altsyncram:ram_block|altsyncram_e891:auto_generated|ram_block1a6~porta_address_reg0
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[6]
From Clock     : DMA_CLOCK
To Clock       : DMA_CLOCK
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_WRITE'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst3|lpm_ff:lpm_ff_component|dffs[7]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[7]
From Clock     : DMA_WRITE
To Clock       : DMA_WRITE
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_DATA_BIDIR[7]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst71|lpm_ff:lpm_ff_component|dffs[7]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[7]
From Clock     : DMA_DATA_BIDIR[7]
To Clock       : DMA_DATA_BIDIR[7]
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_DATA_BIDIR[1]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst3|lpm_ff:lpm_ff_component|dffs[7]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[7]
From Clock     : DMA_DATA_BIDIR[1]
To Clock       : DMA_DATA_BIDIR[1]
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_DATA_BIDIR[3]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst4|lpm_ff:lpm_ff_component|dffs[3]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[3]
From Clock     : DMA_DATA_BIDIR[3]
To Clock       : DMA_DATA_BIDIR[3]
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_DATA_BIDIR[5]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst3|lpm_ff:lpm_ff_component|dffs[7]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[7]
From Clock     : DMA_DATA_BIDIR[5]
To Clock       : DMA_DATA_BIDIR[5]
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_DATA_BIDIR[6]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst3|lpm_ff:lpm_ff_component|dffs[7]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[7]
From Clock     : DMA_DATA_BIDIR[6]
To Clock       : DMA_DATA_BIDIR[6]
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_DATA_BIDIR[0]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst21|lpm_ff:lpm_ff_component|dffs[4]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2]
From Clock     : DMA_DATA_BIDIR[0]
To Clock       : DMA_DATA_BIDIR[0]
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_DATA_BIDIR[2]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[3]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[3]
From Clock     : DMA_DATA_BIDIR[2]
To Clock       : DMA_DATA_BIDIR[2]
Failed Paths   : 10000

Type           : Clock Hold: 'DMA_DATA_BIDIR[4]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[3]
To             : GLOBAL_REGISTERS:inst|lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[3]
From Clock     : DMA_DATA_BIDIR[4]
To Clock       : DMA_DATA_BIDIR[4]
Failed Paths   : 10000

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 110000

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